1. Field of the Invention
The present invention relates to a method for manufacturing a printed wiring board which does not contain a core substrate and into which an electronic component is built.
2. Discussion of the Background
Japanese Laid-Open Patent Publication No. 2006-222164 describes embedding a semiconductor element in an insulation layer to obtain a thinner device without using a core substrate. Japanese Laid-Open Patent Publication No. 2006-222164 describes a method for manufacturing a semiconductor device including mounting a semiconductor element on a support board, forming a buildup layer on the support board and the semiconductor element, and detaching the support board from the buildup layer. In Japanese Laid-Open Patent Publication No. 2006-222164, a manufacturing method including the following process is described (see FIGS. 19 and 20 of Japanese Laid-Open Patent Publication No. 2006-222164). A semiconductor element is covered with an insulation layer. Then, the insulation layer is polished until electrodes of the semiconductor element are exposed, and openings reaching pads on the support board are formed in the insulation layer. Then, via conductors are formed by filling the openings with plating. The contents of this publication are incorporated herein by reference in their entirety.